8.20 电子时钟VHDL程序与仿真
1. 10进制计数器设计与仿真
（1）10进制计数器VHDL程序
--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(3 downto 0);
c:out std_logic);
end counter10;
architecture Behavioral of counter10 is
signal count : std_logic_vector(3 downto 0);
begin
dout <= count;
process(clk,reset,din)
begin
if reset='0'then
count <= din ;
c<='0';
elsif rising_edge(clk) then
if count = "1001" then
count <= "0000";
c<='1';
else
count <= count+1;
c<='0';
end if;
end if;
end process;
end Behavioral;
（2）10进制计数器仿真
2. 6进制计数器设计与仿真
（1）6进制计数器VHDL程序
--文件名：counter6.vhd。
--功能：6进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter6 is
Port ( clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(2 downto 0);
c:out std_logic);
end counter6;
architecture Behavioral of counter6 is
signal count : std_logic_vector(2 downto 0);
begin
dout <= count;
process(clk,reset,din)
begin
if reset= '0' then
count <= din;
c<='0';
elsif rising_edge(clk) then
if count="101" then
count<="000";
c<='1';
else
count<=count+1;
c<='0';
end if;
end if;
end process;
end Behavioral;
（2）6进制计数器仿真
3. 6进制计数器设计与仿真
（1）24进制计数器VHDL程序
--文件名：counter24.vhd。
--功能：24进制计数器。
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
Port ( clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(5 downto 0);
dout : out std_logic_vector(5 downto 0));
end counter24;
architecture Behavioral of counter24 is
signal count : std_logic_vector(5 downto 0);
begin
&nb
