sp; dout <= count;
process(clk,reset,din)
begin
if reset= '0' then
count <= din;
elsif rising_edge(clk) then
if count(3 downto 0)="1001" then
count(3 downto 0)<="0000";
count(5 downto 4)<=count(5 downto 4) +1;
else
count(3 downto 0)<=count(3 downto 0)+1;
end if;
if count="100011" then
count<="000000";
end if;
end if;
end process;
end Behavioral;
（2）24进制计数器仿真
4. 译码器设计
（1）译码器VHDL程序
--文件名：decoder.vhd。
--功能：将4bit二进制数译码，在LED上显示相应数字。
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (din:in std_logic_vector(3 downto 0 ); --四位二进制码输入
dout:out std_logic_vector(6 downto 0) ); --输出LED七段码
end decoder;
architecture Behavioral of decoder is
begin
process(din)
begin
case din is
when "0000" => dout<="0000001";--0
when "0001" => dout<="1001111";--1
when "0010" => dout<="0010010";--2
when "0011" => dout<="0000110";--3
when "0100" => dout<="1001100"; --4
when "0101" => dout<="0100100";--5
when "0110" => dout<="0100000";--6
when "0111" => dout<="0001111";--7
when "1000" => dout<="0000000";--8
when "1001" => dout<="0000100";--9
when others => dout<="1111111";
end case;
end process;
end Behavioral;
5. 顶层设计与仿真
（1）顶层设计VHDL程序
--文件名：clock.vhd。
--功能：时钟的顶层设计。
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( clk : in std_logic; --1Hz
reset : in std_logic; --复位信号
dins : in std_logic_vector(6 downto 0);--秒钟预置
dinm : in std_logic_vector(6 downto 0);--分钟预置
dinh : in std_logic_vector(5 downto 0);--时钟预置
secondl: out std_logic_vector(6 downto 0);--秒钟低位输出
secondh: out std_logic_vector(6 downto 0); --秒钟高位输出
minutel: out std_logic_vector(6 downto 0); --分钟低位输出
minuteh: out std_logic_vector(6 downto 0); --分钟高位输出
hourl: out std_logic_vector(6 downto 0); --小时低位输出
hourh: out std_logic_vector(6 downto 0)); --小
