乐曲硬件演奏电路设计《EDA技术与VHDL》实验报告一、实验设计要求 学习利用实验6-3的数控分频器设计硬件乐曲演奏电路,即设计电子琴,硬件测试可用实验电路模式3。二、设计原理 主系统由三个模块组成，有TONETABA.VHD,NOTETABS.VHD和SPCAKERA.VHD,三、实验程序library ieee;--songer主程序use ieee.std_logic_1164.all;entity songer is port(clk12mhz:in std_logic; clk8hz:in std_logic; code1:out std_logic_vector(3 downto 0); high1:out std_logic; spkout:out std_logic); end;architecture one of songer is component notetabs port(clk:in std_logic; toneindex:out std_logic_vector(3 downto 0)); end component; component tonetaba port(index:in std_logic_vector(3 downto 0); code:out std_logic_vector(3 downto 0); high:out std_logic; tone:out std_logic_vector(10 downto 0)); end component; component speakera port(clk:in std_logic; tone:in std_logic_vector(10 downto 0); spks:out std_logic); end component; signal tone:std_logic_vector(10 downto 0); signal toneindex:std_logic_vector(3 downto 0);beginu1:notetabs port map(clk=>clk8hz,toneindex=>toneindex);u2:tonetaba port map(index=>toneindex,tone=>tone,code=>code1,high=>high1);u3:speakera port map(clk=>clk12mhz,tone=>tone,spks=>spkout);end;library ieee;--speaker程序 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speakera is port( clk:in std_logic; tone:in std_logic_vector(10 downto 0); spks:out std_logic);end;architecture one of speakera is signal preclk,fullspks:std_logic;begindivideclk:process(clk) variable count4:std_logic_vector(3 downto 0); begin preclk<='0'; if count4=15 then preclk<='1';count4:="0000"; elsif clk'event and clk='1' then count4:=count4+1; end if;74
乐曲硬件演奏电路设计四、编译及仿真结果 仿真波形：（1） 若图片无法显示请联系QQ3710167,本论文免费,转发请注明源于www.lwfree.cn（2） 五、总结在做乐曲硬件演奏电路时，先生成。Mif文件，产生data。rom。实验中因为引脚锁定刚开始无法出音乐。end process;genspks:process(preclk,tone) variable count11:std_logic_vector(10 downto 0); begin if preclk'event and preclk='1' then if count11=16#7FF# then count11:=tone;fullspks<='1'; else count11:=count11+1;fullspks<='0';end if; end if;end process;delayspks:process(fullspks) variable count2:std_logic; begin if fullspks'event and fullspks='1' then count2:=not count2; if count2='1' then spks<='1'; else spks<='0'; end if; end if;end process;end;
library ieee;--notetabs程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity notetabs is port(clk:in std_logic; toneindex:out std_logic_vector(3 downto 0));end;architecture one of notetabs iscomponent music1_romend;
library ieee;-- tonetaba程序use ieee.std_logic_1164.all;entity tonetaba is port(index:in std_logic_vector(3 downto 0); code:out std_logic_vector(3 downto 0); high:out std_logic; tone:out std_logic_vector(10 downto 0));end;architecture one of tonetaba isbeginsearch:process(index);when "1100"=>tone<="11001010110"; code<="0101";high<='0';when "1101"=>tone<="11010000100"; code<="0110";high<='0';when "1111"=>tone<="11011000000"; code<="0001";high<='0';when others=>null;end case;end process;end;
