基于CPLD的数字频率计的设计
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资料包括： 论文(33页16069字) 程序 图纸 外文翻译
说明：
基于CPLD的频率计的设计
摘要：
数字频率计是一种基本的测量仪器。它被广泛应用与航天、电子、测控等领域。本设计方案的基本思想是分为五个模块来实现其功能，即整个数字频率计系统分为分频模块、防抖电路、计数模块、锁存器模块和显示模块等几个单元，并且分别用VHDL对其进行编程，实现了闸门控制信号、计数电路、锁存电路、位选电路、段选电路、显示电路等。而且，本设计方案还要求被测输入信号的频率范围自动切换量程，控制小数点显示位置，并以十进制形式显示。本文详细论述了利用VHDL语言设计，并在EDA工具的帮助下，用CPLD实现数字频率计的设计原理及相关程序。CPLD编程特点是：无论底层还是顶层文件均用VHDL语言编写，避免了用电路图设计时所引起的毛刺现象；改变了以往数字电路小规模多器件组合的设计方法。整个频率计设计在一块CPLD芯片上，与用其他方法做成的频率计相比，体积更小，性能更可靠。频率计的测频范围：10KHz～9.9MHz。该设计方案通过了MAX+PLUSⅡ软件仿真、硬件调试和软硬件综合测试。
关键词：数字频率计；电子设计自动化；硬件描述语言；CPLD
Based on the frequency of CPLD design
Abstract：
The digital cymometer is a kind of basic measuring instrument. It is widely used in such fields as the spaceflight , electron , observing and controlling ,etc.. According to digital basic principle of cymometer, basic thought, this text of design plan to divide into five pieces of module realize his function, namely whole digital cymometer system divide into frequency division module , is it tremble circuit , count module , latch module and show such several units as module ,etc. to defend, carry on programming with VHDL to it separately , realize gate control signal , count circuit , location select circuit , section select circuit , show the circuit ,etc.. And, this design plan also requires , are examined the switching over amount automatically of frequency range of the input signal Cheng, control the decimal point and show the position, and show in the form of the decimal system..This article discusses digital cymometer design principles and procedure by using VHDL haraware descriptive programming.EDA tools and on the basis of grand scale programmable logic device CPLD.The main point of this article is that both bottom’s and top’s documents are written by VHDL programming,which avoids “rough phenomenon”,a phenomenon caused by usuing electric circuit picture style design.This software procedure is different from traditional digital circuit design at small scale and composed of many devices.Intead,the whole cymometer is designed on a CPLD and is composed of a decimal system cymometer.Compared with other cymometer ,it is small in volume and reliable function. The frequency is designed from 10KHz to 9.9MHz.The whole system passes the debugging in Max+plusⅡsoftware simulation,software and hardware parts.
Key words： THE DIGITAL CYMOMETER ；EDA ；VHDL； CPLD 目录：
目录
摘要： 1
ABSTRACT： 1
1.绪论 2
1.1 概述 2
2.CPLD简介 3
2.1 CPLD器件结构 3
2.2 ALTERA CPLD器件简述 4
2.3 CPLD的编程工艺 4
2.3.1 EPROM工艺 4
2.3.2 EEROM工艺 4
2.3.3 FLASH工艺 4
2.4 新技术的应用 5
2.4.1 CPLD的在系统编程技术 5
2.4.2 片内存储器和其他片内逻辑 5
2.4.3 低电压、低功耗系列芯片 5
2.4.4 IP的使用和嵌入式模块 5
2.4.5混合编程技术 5
3.MAX+PLUSⅡ软件的介绍 6
3.1 MAX+PLUSⅡ的概述 6
3.2 MAX+PLUSⅡ的功能简介 6
4.频率计的概述 7
4.1 频率计的基本组成 7
4.2频率计的分类 7
4.3频率计的技术指标 7
4.4频率计的基本工作原理 8
4.5频率计的技术指标及误差分析 8
5.频率计的设计 10
5.1频率计的设计任务及要求 10
5.2设计实现 10
5.2.1顶层系统设计 10
5.2.2频率计设计流程图 11
5.3功能模块设计 11
5.3.1 分频模块 11
5.3.2 计数模块 11
5.3.3 锁存器模块 11
5.3.4显示模块 11
5.3.5防抖动模块 11
5.4各模块基于VHDL的设计方法 12
5.5顶层文件编写 14
5.6程序说明 14
5.7系统仿真 14
5.8下载验证 15
6.结论 16
参考文献 17
附录一 源程序 18
附录二 英文文献翻译 25
致 谢 30
资料包括： 论文(33页16069字) 程序 图纸 外文翻译
说明：
基于CPLD的频率计的设计
摘要：
数字频率计是一种基本的测量仪器。它被广泛应用与航天、电子、测控等领域。本设计方案的基本思想是分为五个模块来实现其功能，即整个数字频率计系统分为分频模块、防抖电路、计数模块、锁存器模块和显示模块等几个单元，并且分别用VHDL对其进行编程，实现了闸门控制信号、计数电路、锁存电路、位选电路、段选电路、显示电路等。而且，本设计方案还要求被测输入信号的频率范围自动切换量程，控制小数点显示位置，并以十进制形式显示。本文详细论述了利用VHDL语言设计，并在EDA工具的帮助下，用CPLD实现数字频率计的设计原理及相关程序。CPLD编程特点是：无论底层还是顶层文件均用VHDL语言编写，避免了用电路图设计时所引起的毛刺现象；改变了以往数字电路小规模多器件组合的设计方法。整个频率计设计在一块CPLD芯片上，与用其他方法做成的频率计相比，体积更小，性能更可靠。频率计的测频范围：10KHz～9.9MHz。该设计方案通过了MAX+PLUSⅡ软件仿真、硬件调试和软硬件综合测试。
关键词：数字频率计；电子设计自动化；硬件描述语言；CPLD
Based on the frequency of CPLD design
Abstract：
The digital cymometer is a kind of basic measuring instrument. It is widely used in such fields as the spaceflight , electron , observing and controlling ,etc.. According to digital basic principle of cymometer, basic thought, this text of design plan to divide into five pieces of module realize his function, namely whole digital cymometer system divide into frequency division module , is it tremble circuit , count module , latch module and show such several units as module ,etc. to defend, carry on programming with VHDL to it separately , realize gate control signal , count circuit , location select circuit , section select circuit , show the circuit ,etc.. And, this design plan also requires , are examined the switching over amount automatically of frequency range of the input signal Cheng, control the decimal point and show the position, and show in the form of the decimal system..This article discusses digital cymometer design principles and procedure by using VHDL haraware descriptive programming.EDA tools and on the basis of grand scale programmable logic device CPLD.The main point of this article is that both bottom’s and top’s documents are written by VHDL programming,which avoids “rough phenomenon”,a phenomenon caused by usuing electric circuit picture style design.This software procedure is different from traditional digital circuit design at small scale and composed of many devices.Intead,the whole cymometer is designed on a CPLD and is composed of a decimal system cymometer.Compared with other cymometer ,it is small in volume and reliable function. The frequency is designed from 10KHz to 9.9MHz.The whole system passes the debugging in Max+plusⅡsoftware simulation,software and hardware parts.
Key words： THE DIGITAL CYMOMETER ；EDA ；VHDL； CPLD 目录：
目录
摘要： 1
ABSTRACT： 1
1.绪论 2
1.1 概述 2
2.CPLD简介 3
2.1 CPLD器件结构 3
2.2 ALTERA CPLD器件简述 4
2.3 CPLD的编程工艺 4
2.3.1 EPROM工艺 4
2.3.2 EEROM工艺 4
2.3.3 FLASH工艺 4
2.4 新技术的应用 5
2.4.1 CPLD的在系统编程技术 5
2.4.2 片内存储器和其他片内逻辑 5
2.4.3 低电压、低功耗系列芯片 5
2.4.4 IP的使用和嵌入式模块 5
2.4.5混合编程技术 5
3.MAX+PLUSⅡ软件的介绍 6
3.1 MAX+PLUSⅡ的概述 6
3.2 MAX+PLUSⅡ的功能简介 6
4.频率计的概述 7
4.1 频率计的基本组成 7
4.2频率计的分类 7
4.3频率计的技术指标 7
4.4频率计的基本工作原理 8
4.5频率计的技术指标及误差分析 8
5.频率计的设计 10
5.1频率计的设计任务及要求 10
5.2设计实现 10
5.2.1顶层系统设计 10
5.2.2频率计设计流程图 11
5.3功能模块设计 11
5.3.1 分频模块 11
5.3.2 计数模块 11
5.3.3 锁存器模块 11
5.3.4显示模块 11
5.3.5防抖动模块 11
5.4各模块基于VHDL的设计方法 12
5.5顶层文件编写 14
5.6程序说明 14
5.7系统仿真 14
5.8下载验证 15
6.结论 16
参考文献 17
附录一 源程序 18
附录二 英文文献翻译 25
致 谢 30