基于EDA技术的智力竞赛抢答器的设计

论文编号:JD856 附开题报告,任务书,外文翻译,原理图,论文字数:15131,页数:35

摘　要:　
抢答器作为一种工具，已经广泛应用于各种智力和知识竞赛场合。但是抢答器的使用频率较低，且有的要么制作复杂，要么可靠性低，减少兴致。作为一个单位若专购一台抢答器虽然在经济上可以承受，但每年使用的次数极少，往往因长期存放使抢答器损坏，再购置一台新的就会影响活动的开展，因此设计了本抢答器。
本设计是以八路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。该抢答器的设计利用Protel99完成了原理图设计、利用VHDL完成了控制主电路设计，具有数字显示电路、倒计时显示电路、编码译码电路功能，并利用MAX＋PLUSⅡ工具软件完成了编译仿真验证；硬件选择ALTERA公司的EPF10K10LC84芯片来实现抢答器的系统功能，该抢答器具有很强的功能扩充性，应用效果良好。
关键词:　电子设计自动化；抢答器；硬件描述语言；仿真

Vies to answer the first design based on the EDA technology''s intelligence competition

Abstract:　
With a tool for answer devices, which has been widely used in all kinds of intelligence and knowledge contest occasions. But answer devices is used for lower frequency, and some production complex or low reliability, and reduced interest. As a unit, if the purchase is a answer devices. Although the economy can bear, each year the number is extremely small, because often the long-term storage causes to answer devices damage, the purchase of a mew one, the activities will be affected, so this answer devices is designed.
This design is eight roads Answer devices as the basic concept. From practical application, Complex programmable logic devices (CPLD) were used to design a competitive answer machine by use of EDA technique. The design of the Answer devices the use of Protel99 to complete the schematic diagram and the use of VHDL to complete the main control circuit design, including digital display circuit, countdown display and coding and decoding circuits. The ALTERA MAX+PLUS Ⅱsoftware tool was used for compilation emulation verification. The ALTERA EPF10K10LC84 was chosen in the hardware system to realize the system functions. The design of the competitive answer machine is easily expandable and provides good application results.
Key words: 　EDA; Answer devices; VHDL; Simulation

摘要 Ⅰ
目次 Ⅲ
1 绪论 1
1.1 课题研究的相关背景 1
1.2 EDA技术的发展趋势 1
1.3 EDA技术的应用场合 2
1.4 国内外研究现状 2
1.5 选题的目的和意义 2
1.6 抢答器目前存在的问题 3
2 课题任务 3
2.1 设计内容 3
2.2 设计参数 4
2.3 抢答器系统设计思路和设计过程 4
3 系统所用器件介绍 5
3.1 FLEX10K系列芯片 5
3.1.1 FLEX 10K可编程逻辑器件概述 5
3.1.2 FPXA10K芯片的内部结构及其主要特点 5
3.1.3 EPF10K10LC84芯片的主要性能 7
       3.1.4 EPF10K10LC84芯片的引脚图  9
3.2优先编码器 74LS148 9
3.3与非门和非门 10
3.3.1 二输入与非门74LS00 10
3.3.2 八输入与非门 74LS30 11
3.3.3 非门74LS04 11
3.4 BCD显示译码驱动器 12
3.5 74LS175锁存器 14
3.6 计数器 15
3.6.1 十进制可逆计数器 ――74LS192 15
3.6.2 4位二进制/十进制加减计数器――CC4029 16
3.7 555定时器 17
4 电路设计 20
4.1 抢答器的工作流程 20
4.2 抢答器的主要组成及其功能 21
4.2.1 抢答控制电路的原理分析 22
4.2.2 定时电路的原理分析 23
4.2.3 计分电路的原理分析 24
5 基于VHDL的设计 24
5.1 VHDL实体设计 25
5.2 抢答器鉴别电路程序及其仿真图 26
5.3 计分电路程序及其仿真图 28
5.4 定时电路程序及其仿真图 30
5.5 译码电路程序及其仿真图 32
6 结论 33
参 考 文 献 34
致 谢 35